As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Historically, testability is an afterthought in the design process. But heightening complexity of chip designs, and especially SoCs, forces testability (and manufacturability) to take a more central ...

Boundry-scan testing (IEEE1149.1/JTAG) is a novel procedure for some test engineers and technicians. But ScanWorks Interconnect Development Station version 3.4 from Asset Intertech should ease their ...

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these ...